High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by stacking memory dies (or “dice”) vertically and interconnecting the memory dies using through-silicon (or through-substrate) vias (TSVs). Benefits of the 3D memory devices include shorter interconnects which reduce signal delays and power consumption, a large number of vertical vias between layers which allow wide bandwidth buses between functional blocks in different layers, and a considerably smaller footprint. Thus, the 3D memory devices contribute to higher memory access speed, lower power consumption and chip size reduction. Example 3D memory devices include Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM). For example, High Bandwidth Memory (HBM) is a type of memory including a high-performance dynamic random access memory (DRAM) interface die and vertically stacked DRAM dies.
After assembly of the stacked memory dies and interface die, the memory device cannot be easily disassembled in the event one or more of the stacked memory dies become inoperable. A memory die may become inoperable for a variety of reasons, for example, one or more of the circuits of the memory die do not function properly, memory cells of the memory die are defective and cannot correctly and/or adequately store data, etc. Although each die typically includes a limited amount of redundant memory circuits for repairing defective memory cells, the redundant memory circuits may not be capable of repairing all defective memory cells of the memory die, and additionally, inoperable circuits of a memory die may not be repairable. As a result of one or more inoperable memory dies assembled in the stack, if an inoperable die cannot be repaired in place, the entire memory device is scrapped, even if several of or all other memory dies in the stack and the interface are operable.
It may be desirable to provide repairability to memory devices having a plurality of memory dies and an interface die in order to recover an operable memory device although one or more of the memory dies is inoperable.